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| 19-5266; Rev 5/10 DS1642 Nonvolatile Timekeeping RAM www.maxim-ic.com FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Clock Registers are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power Access Times of 85ns and 100ns Quartz Accuracy 1 Minute a Month at +25C, Factory Calibrated BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Up to 2100 Power-Fail Write Protection Allows for 10% VCC Power Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time UL Recognized PIN CONFIGURATION TOP VIEW A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC A8 A9 WE OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 DS1642 23 22 21 20 19 18 17 16 15 14 13 ENCAPSULATED DIP ORDERING INFORMATION PART DS1642-85+ DS1642-100+ VOLTAGE RANGE (V) 5.0 5.0 TEMP RANGE 0C to +70C 0C to +70C PIN-PACKAGE TOP MARK 24 EDIP (0.720a) DS1642+85 24 EDIP (0.720a) DS1642+100 +Denotes a lead(Pb)-free/RoHS-compliant package. A "+" indicates a lead(Pb)-free product. The top mark will include a "+" symbol on lead-free devices. 1 of 11 DS1642 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 19 22 23 9 10 11 13 14 15 16 17 12 18 20 21 24 NAME A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND CE OE WE VCC FUNCTION Address Input Data Input/Output Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input DESCRIPTION The DS1642 is a 2k x 8 nonvolatile static RAM and a full-function real-time clock (RTC), both of which are accessible in a bytewide format. The nonvolatile time keeping RAM is pin and function equivalent to any JEDEC-standard 2k x 8 SRAM. The device can also be easily substituted in ROM, EPROM, and EEPROM sockets, providing read/write nonvolatility and the addition of the real-time clock function. The real-time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1642 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. 2 of 13 DS1642 CLOCK OPERATIONS-READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock status is reset. Updating occurs within a second after the read bit is written to 0. Figure 1. DS1642 BLOCK DIAGRAM Table 1. TRUTH TABLE VCC 5V 10% <4.5V > VBAT VIH VIL VIL VIL X X X X VIL VIH X X X VIL VIH VIH X X MODE Deselect Write Read Read Deselect Deselect DQ High-Z Data In Data Out High-Z High-Z High-Z POWER Standby Active Active Active CMOS Standby Data Retention Mode 3 of 13 DS1642 SETTING THE CLOCK The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the DS1642 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, and OE low) and address for seconds register remain valid and stable. CLOCK ACCURACY The DS1642 is guaranteed to keep time accuracy to within 1 minute per month at 25C. Dallas Semiconductor calibrates the clock at the factory by using special calibration nonvolatile-tuning elements. The DS1642 does not require additional calibration and temperature deviations will have a negligible effect in most applications. For this reason, methods of field clock calibration are not available and not necessary. Table 2. REGISTER MAP-BANK1 ADDRESS 7FF 7FE 7FD 7FC 7FB 7FA 7F9 7F8 OSC = STOP BIT W = WRITE BIT B7 -- X X X X X OSC W B6 -- X X FT X -- -- R B5 -- X -- X -- -- -- X DATA B4 B3 -- -- -- -- -- -- X X -- -- -- -- -- -- X X B2 -- -- -- -- -- -- -- X B1 -- -- -- -- -- -- -- X B0 -- -- -- -- -- -- -- X FUNCTION Year Month Date Day Hour Minutes Seconds Control 00-99 01-12 01-31 00-23 00-59 00-59 00-59 A R = READ BIT X = UNUSED FT = FREQUENCY TEST Note: All indicated "X" bits are not used but must be set to "0" during write cycle to ensure proper clock operation. 4 of 13 DS1642 RETRIEVING DATA FROM RAM OR CLOCK The DS1642 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1642 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE When VCC is within nominal limits (VCC > 4.5V) the DS1642 can be accessed as described above by read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished internally by inhibiting access via the CE signal. When VCC falls below the level of the internal battery supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal level. BATTERY LONGEVITY The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of VCC power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1642 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. 5 of 13 DS1642 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground.....................................................-0.3V to +6.0V Operating Temperature Range......................................................0C to +70C (noncondensing) Storage Temperature Range................................................... -40C to +85C (noncondensing) Lead Temperature (soldering, 10 seconds) Note: Hand or wave-soldered only (Note 6) ............. . . . . . . . . . ..................... . . . . . . .....+260C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Voltage (All Inputs) Logic 0 Voltage (All Inputs) SYMBOL VIH VIL MIN 2.2 -0.3 TYP MAX VCC + 0.3 0.8 UNITS V V NOTES 1 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Active Supply Current TTL Standby Current ( CE = VIH) CMOS Standby Current ( CE < VCC - 0.2V) Input Leakage Current (Any Input) I/O Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT = +2.1mA) Write Protection Voltage SYMBOL ICC ICC1 ICC2 IIL IOL VOH VOL VPF 4.25 4.37 -1 -1 2.4 0.4 4.50 V MIN TYP 15 1 1 MAX 50 3 3 +1 +1 UNITS mA mA mA A A 1 1 1 NOTES 2, 3 2, 3 2, 3 6 of 13 DS1642 AC CHARACTERISTICS--READ CYCLE PARAMETER Read Cycle Time Address Access Time CE CE SYMBOL tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH 85ns ACCESS MIN MAX 85 85 5 85 30 5 45 30 5 100ns ACCESS MIN MAX 100 100 5 100 35 5 55 35 5 UNITS ns ns ns ns ns ns ns ns ns NOTES to DQ Low-Z Access Time Data Off Time to DQ Low-Z Access Time Data Off Time CE OE OE OE Output Hold from Address READ CYCLE TIMING DIAGRAM 7 of 13 DS1642 AC CHARACTERISTICS--WRITE CYCLE (VCC = 5.0V 10, TA = 0C to +70C.) PARAMETER Write Cycle Time Address Setup Time WE CE SYMBOL tWC tAS tWEW tCEW tDS tDH tAH tWEZ tWR 85ns ACCESS MIN MAX 85 0 65 70 35 0 5 30 5 100ns ACCESS MIN MAX 100 0 70 75 40 0 5 35 5 UNITS ns ns ns ns ns ns ns ns ns NOTES Pulse Width Pulse Width Data Setup Time Data Hold Time Address Hold Time WE Data Off Time Write Recovery Time 8 of 13 DS1642 WRITE CYCLE TIMING DIAGRAM--WRITE-ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM--CHIP-ENABLE CONTROLLED 9 of 13 DS1642 POWER-UP/POWER-DOWN AC CHARACTERISTICS (TA = 0C to +70C) PARAMETER CE SYMBOL tPD tF tFB tR tREC tDR MIN 0 300 10 0 TYP MAX UNITS s s s s NOTES or WE at VIH Before Power-Down VCC Fall Time: VPF (MAX) to VPF (MIN) VCC Fall Time: VPF (MIN) to VBAT VCC Rise Time: VPF (MIN) to VPF (MAX) Power-up Recover Time Expected Data Retention Time (Oscillator On) 35 10 ms years 4, 5 POWER-UP/POWER-DOWN WAVEFORM TIMING CAPACITANCE (TA = +25C) PARAMETER Capacitance on All Pins (except DQ) Capacitance on DQ Pins SYMBOL CIN CO MIN TYP MAX 7 10 UNITS pF pF NOTES 10 of 13 DS1642 AC TEST CONDITIONS Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltages are referenced to ground. 2) Typical values are at 25C and nominal supplies. 3) Outputs are open. 4) Data retention time is at 25C. 5) Each DS1642 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 6) Real-time clock modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal. 11 of 13 DS1642 PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 EDIP PACKAGE CODE MDF24+1 DOCUMENT NO. 21-0245 DS1642 24-PIN PACKAGE PKG DIM. A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 24-PIN MIN MAX 1.270 1.290 37.34 37.85 0.675 0.700 17.15 17.78 0.315 0.335 8.00 78.51 0.075 0.105 1.91 2.67 0.015 0.030 0.38 0.76 0.140 0.180 3.56 4.57 0.090 0.110 2.29 2.79 0.590 0.630 14.99 16.00 0.010 0.018 0.25 0.45 0.015 0.025 0.43 0.58 12 of 13 DS1642 REVISION HISTORY REVISION DATE 5/10 DESCRIPTION Removed TinLead and -70 (70ns) and added -85 (85ns) in the Ordering Information table; reduced the Absolute Maximum Ratings max voltage; updated the soldering information; updated AC timing to include 85ns PAGES CHANGED 1, 6, 7, 8 13 of 13 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Maxim Integrated Products, Inc. |
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